1. Field of the Invention
This invention generally relates to the field of serial data communications systems, and more particularly relates to a data assisted serial link decoder using oversampling that is suitable for use in high speed signalling such as for video serial link communications.
2. Description of Related Art
A variety of electronic devices, such as computers, monitors, flat panel displays, wireless communication devices, to name just a few, communicate data over communication links utilizing high speed electronic signals, e.g., clock signals, video signals, spread spectrum and digital wireless communication signals, etc. A predominant trend in electronic devices is the use of digital signals. As is well known to those of ordinary skill in the art, there are many advantages to representing electronic signals in digital signal form in many such electronic devices.
In particular, a digital display, such as an LCD display, receives video data from a graphics host, such as a computing platform, via a serial communication link. This serial link typically is implemented in a cable bundle that is interconnected between an output of a graphics host interface and an input of a digital display interface. The signalling across the serial link is considered an analog signal that besides the encoding of data from the graphics host, typically picks up other undesirable distortion and noise signals. The composite signal, including distortion and noise, received at the input of the digital display interface normally must be filtered, reconstructed, and decoded to recover the transmitted data and deliver it to the digital video display monitor circuits to maintain high quality in the displayed video images at the digital display.
Conventional implementations of video signal reconstruction have attempted to reconstruct a digital representation of an analog video signal as follows. An Analog-to-Digital Converter (ADC) module is driven with a sampling clock signal to sample points in an analog video signal to identify the leading and trailing edges of any signal transition in an analog video signal. The edges of a signal transition normally are not desirable sampling points for sampling the voltage amplitude of the particular video pixel (picture element). It is desirable to sample the signal in the flat region (between the edges) of the signal transition where the voltage level is stable and may be better determined from the sample point. Prior art methods drive the ADC to sample at a point in the signal that is just before the trailing edge of the signal, where the flat region was expected to be most likely stable. This sampling point is selected simply to avoid the leading and trailing edges. However, any clock jitter, for example, tends to defeat this sampling method because it is very difficult to select a sampling clock rate that avoids the trailing edge of the signal transition while intermittent jitter keeps moving the trailing edge of a signal transition relative to a time reference. Additionally, other sources of noise may be present during the flat region of the signal and a sample taken by the ADC during this noise signal will possibly provide a false measurement of signal level.
In one particular example, a computer graphics controller using frame buffer data transmits a digital video signal to a Digital-to-Analog Converter (DAC) module to provide an analog video signal at an output of a computer graphics interface. This output video signal is utilized to drive a video monitor. The video signal is coupled to an interface of a video monitor typically via a cable. The transmission via the cable medium tends to pick up noise signals and adds distortion to the analog video signal. For example, besides distortion due to capacitive and inductive effects of the cable medium, this distortion may also include jitter from the output of the computer graphics interface. On the other side of this cable medium, when receiving the analog video signal including all the noise and distortion signals, a video interface for the video monitor couples the analog video signal to a ADC module. However the graphics controller clock is not transmitted to the video monitor. For a digital video monitor, this clock must be regenerated and the sample phase adjusted to synchronize the ADC samples with the original graphics controller digital clock period. Regrettably, conventional ADC implementations have not been very successful at removing most of the noise and distortion signals from the pure analog video signal. The resulting digital representation of the video signal may include some of the noise and distortion signals, which are particularly detrimental to the quality of the video image if the clock regeneration and phase adjustment are inaccurate.
An industry initiative attempts to address some of these issues in the delivery of high speed video signals across serial data links by utilizing a signalling protocol called Transition Minimized Differential Signalling (TMDS). A TMDS transmitter, at a graphics host, is communicatively coupled to a TMDS receiver, at a digital display, via a multi-channel serial communication link (a TMDS Link). Data code words and control code words are serially transmitted across the link to deliver data while maintaining the clock signalling synchronized between the graphics host and the digital display. Bit synchronization is normally first obtained, and then a word synchronization process attempts to synchronize code word recovery to be able to reliably deliver video information, e.g., pixel data, from the graphics host across the TMDS Link and to the digital display.
However, although the industry standard defines the signalling protocol requirements and provides a recommended signal encoding algorithm, the implementation of signal recovery and code word decoding is essentially left for ad hoc implementation by manufacturers of digital displays. Lack of precise signal recovery, including removal of distortion and noise signals and accurate code word decoding, unfortunately, results in noise and distortion signals tending to pass through and affect the digital representation of the video signal, e.g., the pixel data, in the digital display. This reduces the quality of a video image, and leads to the loss of image information, that is presented via a video monitor display to a user. The result is a lower opinion of the quality of the video monitor system and a reduced commercial viability of such products.
This reduced recovered signal quality and lost information can seriously impact other communication applications as well. For example, distorted or lost information in a wireless communication signal can significantly impact or even destroy a wireless communication across a wireless communication link.
Therefore a need exists to overcome the problems with the prior art as discussed above, and particularly for a communication system utilizing a data assisted serial link decoder that is suitable for use in high speed signalling systems such as for video serial link communications.